Data-Level Parallelism Oriented Memory Access and On-Chip Buffering Mechanisms for a Loop Accelerator
نویسندگان
چکیده
منابع مشابه
On-chip Self Testing using BIST-oriented Random Access Memory
The increased circuit density in today’s integrated circuits demands for efficient and low cost testing as compared to the testing of logic with external test equipment. The Built-In Self Test (BIST) architecture provides the self-testing of logic circuit but is not at the positive extreme in delivering deterministic and limited test vectors and storage and compression of output test responses....
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ژورنال
عنوان ژورنال: Journal of Physics: Conference Series
سال: 2021
ISSN: 1742-6588,1742-6596
DOI: 10.1088/1742-6596/1914/1/012047